Gain control circuits



June 10, 1941. x w. J. MJORLOCK 2,245,353

GAIN CONTROL CIRCUITS Filed June 14, 195$ 2 Sheets-Sheet 1 mar/m2 40/90CUAV/f ZSnventor n 10, 1941. w. J. MORLOCK GAIN\CONTROL CIRCUIIS '"FildJune '14, 1938 2 Sheets-Sheet 2 .i[ ax up M Gtfomeg Patented June 10,1941 STATES HQE GAIN CONTROL CIRCUITS of Delaware Application June 14,1938, Serial No. 213,571

4 Claims.

This invention relates to gain control circuits such as are applicableto public announcement and other radio or audio frequency amplifyingsystems, and has for its principal object the provision of an improvedcircuit and method of operation whereby a higher average acousticaloutput may be obtained from an amplifier without increased rating andwithout overload from excessive signal input.

In accordance with the present invention, there are provided a pluralityof gain control circuits one of which gradually compresses the output asthe signal level increases up to a point near the normal rating of theamplifier and another of which rapidly compresses the output beyond thispoint. Under these conditions, signals of a very low level are highlyamplified, the amplifier gain decreases as the input signal levelincreases, a higher average acoustic output is realized Withoutincreasing the peak rating of the equipment, and the output at highsignal level is compressed to an extent which prevents overloading.

The invention will be better understood from the following descriptionconsidered in connection with the accompanying drawings and its scope isindicated by the appended claims.

Referring to the drawings Figure 1 is a wiring diagram of an amplifyingsystem to which the invention is applied,

Figure 2 is an explanatory diagram relating to the operation of thesystem of Fig. 1, and

Figure 3 is a wiring diagram of a resistance coupled amplifier systeminvolving the invention.

The system of Fig. 1 includes input terminals l-l| and output terminalsl2--I3 between which signals are transmitted through an amplifyingchannel including a coupling transformer M, a pair of parallel connectedtubes l5-!5 which are of the exponential characteristic type, a couplingcapacitor 11, a single tube stage I 8, a coupling transformer is, apush-pull stage 2fi-2l and a coupling transformer 22. Power foroperating these various stages of the amplifying channel is derived fromthe direct current supply terminals 23 and 24, the negative side of thispower supply line being grounded. It should be understood that theparallel connected tubes l5l6 and the push-pull connected tubes 2ll2|may be replaced by a single triode without altering theoperation of thesystem.

The input circuit of the tubes l5-l6 includes (1) the secondary windingof the transformer 14 through which the signal is applied, (2) aresistor 25 through which a gradually increasing volume compressionpotential and an anti-overload bias derived through a lead 28 areapplied and (3) a bleeder resistor 25 from a part of which a bias isderived through the lead 28 to a diode 36.

The volume compression lbias potential of the resistor 25 is derivedfrom the secondary winding of the transformer 22 through relatively lowvoltage leads 28-36, a diode 3i and a switch 32 and the lead't'l. Acapacitor '33 is connected in shunt to the resistor 25 for timing theaction of this volume control circuit.

The anti-overload bias of the resistor 25 is derived from the relativelyhigh voltage secondary leads 3d-35 through a diode 36, the lead 28, thelower section of the resistor 26 and the lead 37. Since this overloadcontrol circuit includes the lower section of the resistor 25, it issubjected to a bias potential which allows current to fiow through thediode 36 only when the signal output attains a predetermined high value.

It should be noted that the resistor 26 and the cathode lead resistors38 and 39 are shunted by signal by-pass capacitors 4i), 4! and 42 andthat a direct current stopping condenser 43 is provided in the signaloutput circuit of the amplifier stage i8 which is also provided with anoutput resistor 44 and an input resistor 45.

Fig. 2 illustrates the characteristic operation of the system of Fig. 1,the point 0 being taken as the reference point of the curves D-E, C-Aand A-B. The curve DE will be recognized as the normal characteristicload curve plotted with amplifier input as abscissae and with amplifieroutput as ordinates. Otherwise stated, the curve DE' is the normal loadcurve of the amplifier in the absence of the volume compression andanti-overload control circuits.

The curve C-A is the amplifier load characteristic resulting from thebias potential produced in the resistor 25 of the volume compressioncircuit 29-36, 3! and 3?. Thus, a part of the output signal is fed tothe diode 3|, this signal is rectified by the diode 3i and the rectifiedcurrent flows through the resistor 25. This current will begin flowingat a signal level at least 40 db. below the normal input signal of theamplifier, this signal being represented by the reference numeral 0. Abias voltage is produced in the resistor 25 which forms a part of theinput circuit of the amplifier l5-l6. This amplifier has an exponentialcharacteristic which permits a variation of amplification by changingits grid bias voltage. It is thus apparent that the amplification ofthis amplifier will vary with the potential drop of the resistor 25 andit will amplify less as the signal output level increases. Otherwisestated, the volume is compressed as the output signal level increases.

The curve A--B is the amplifier load charac teristic resulting from thebias potential produced in the resistor 25 by the anti-overload orrelatively high compression circuit 34-35, 36 and 31. The diode 36 hasapplied to its cathode a bias potential derived from the lower sectionof the bleeder resistor 26 through the lead 28. This bias potential isadjusted to equal the signal output voltage applied to the diode 35 whenthe amplifier is delivering its rated output. As the signal outputvoltage applied to the diode must exceed the value of the bias potentialbefore rectification occurs, it follows that no current is deliveredthrough the diode 36 until the amplifier delivers its normal output.This point is indicated at A. At this point, the overload controlcircuit begins to function to add more current to that flowing throughthe resistor 25, thus increasing the bias potential and producing a morerapid compression of the amplifier output.

The system of Fig. 3 accomplishes the same result as the system of Fig.1 but differs therefrom in that the volume compression and overload biaspotentials are applied to different stages of a resistance coupledamplifying channel. This channel includes signal input terminals Ill-l land signal output terminals l2l3 which are in-- terconnected through anamplifier 46, a coupling capacitor ii, an amplifier it and a couplingcapacitor 49.

It will be noted that the amplifiers 46 and 48 are of the pentode typeand that power for operating the amplifying channel is derived from thepower supply terminals 23-24. The input signal is applied to a resistor50 which has its upper terminal connected to the control grid of theamplifier 46 and its lower terminal grounded for alternating currentthrough a capacitor 5!.

Anode-cathode potential is applied to the amplifier 46 from a filterresistor 52 and capacitor 53 through an output resistor 57, a bleederresistor 54-55 partly shunted by a capacitor 56 being provided forproducing a constant bias potential in the amplifier input circuit. Thescreen grid potential of the amplifier 46 is derived from a filterresistor 58 and capacitor 59. The similar connections of the amplifier48 will be understood Without detailed explanation.

From the output circuit of the amplifying channel is derived a controlsignal which is applied to the control circuit terminals 60 and GI.

Connected to the terminals 60 and BI through coupling capacitors 62 and63 and resistors 64 and 65 is a diode double wave rectifier 3| providedwith a cathode lead resistor 66 from which a volume compression biaspotential is applied through a resistor 61 to the control and suppressorgrids of the amplifier stage 45. The application of this bias potentialto both the grids is advantageous in that it makes the amplifier 46operate with an exponential type of load characteristic.

Also coupled to the control terminals 68 and El through capacitors 63and 69 and resistors 10 and H is a diode double Wave rectifier 36provided with a cathode lead resistor 12 from which overload biaspotential is applied through a resistor 13 to the control and suppressorgrids of the amplifier stage 48. For the purpose of preventing the flowof current through the rectifier 36 from affecting the input of theamplifier 48 until the amplifier output has attained normal value, anadjustable part of a bleeder resistor 14 shunted by a capacitor I5 isinterposed in the input circuit. The resistor T2 is shunted by a timingcapacitor 16.

The operation of the system of Fig. 3 is the same as that of Fig, 1, thedouble diode 3| functioning to gradually compress the output as-thesignal level increases and the double diode 36 functioning to preventoverloading of the output circuit.

I claim as my invention:

1. The combination of an amplifier provided with input and outputcircuits, a resistor connected in said input circuit, means for derivingfrom said output circuit and producing in said resistor a bias potentialwhereby the gain of said amplifier is gradually reduced as the signallevel increases to its normal value, means for deriving from said outputcircuit and producing in said resistor a bias potential whereby the gainof said amplifier is reduced more rapidly when the signal level exceedsits normal value, and means for preventing the production of said latterbia potential until said signal level has attained its normal value.

2. The combination of an amplifier provided with input and outputcircuits, a resistor connected in said input circuit, means for derivingfrom said output circuit and producing in said resistor a bias potentialwhereby the gain of said amplifier is gradually reduced as the signallevel increases to its normal value, means for deriving from said outputcircuit and producing in said resistor a bias potential whereby the gainof said amplifier is reduced more rapidly when the signal level exceedsits normal value, and means for timing the relation of the gaincontrolling action of said bias potentials on said input circuit.

3. In a signal amplifying channel including a plurality of amplifyingstages, the combination of an amplifying tube in an initial stage havingan amplification control circuit, means providing a signal outputimpedance for said amplifying channel to which said amplificationcontrol circuit is connected, means providing low signal voltage andhigh signal voltage output connections on said impedance means onopposite sides of said last-named connection, a rectifier for each ofsaid low voltage and high voltage output connections, a common outputresistor for said rectifiers, said amplifier tube having a cathode andsaid resistor being connected between the cathode and said amplificationcontrol circuit, and means providing a delayed potential in circuit withthe rectifiers for the high signal Voltage output connection of a valueto prevent operation of the high voltage rectifiers until the amplifyingchannel delivers a normal signal output level.

4. In an audio frequency amplifier, the combination of an initialamplifying stage comprising an amplifying tube having a cathode and anamplification control electrode, an output transformer for saidamplifier having a secondary provided with low and high signal potentialoutput connections and. a connection common thereto for said controlelectrode, a biasing resistor connected between said last-namedconnection and the cathode, a rectifier connected between each of saidlow and high signal voltage output connections and said resistor wherebysaid resistor provides a common output potential means for saidrectifiers, and means providing a fixed source of delay potential incircuit with said high signal potential rectifiers having a potentialvalue such that said high signal voltage rectifiers are renderedinoperative until a predetermined normal signal output level isattained.

WILLIAM J MORLOCK.

